The present invention relates to a semiconductor device manufacturing method, a semiconductor device manufacturing program, and a semiconductor device manufacturing system each having a pattern design for inserting a repeater for adjusting a signal delay into a wiring(s) of a semiconductor integrated circuit.
In recent years, physical layouts of integrated circuits have been complicated along with miniaturization of semiconductor devices. Processing for generating mask data from the physical layout starts with a layout data on which is outputted after completion of arrangement wiring (a layout based on graphic data). That is to say, optical proximity correction (OPC) processing is executed for a pattern after design rule checking (DRC) processing and schematic inspecting (LVS) processing are carried out for a layout data on which is outputted after completion of the arrangement wiring processing. Also, mask data is generated after completion of the OPC verifying processing.
On the other hand, so-called timing convergence processing, such as RC extracting processing, delay calculating processing, and static timing analyzing (STA) processing, for calculating a parasitic capacitance value and a parasitic resistance value in a semiconductor integrated circuit is executed in parallel with such layout processing.
Recently, a mutual influence between the layout processing side and the timing convergence side has begun to be feared due to the complication of the physical layout described above. For example, when the layout after completion of the detailed wiring is changed, it is necessary to ensure the influence exerted on the timing. Also, in the processing for the timing convergence, it is necessary to confirm whether or not there is an influence exerted on the layout.
In order to cope with the former case of the above two cases, an arrangement wiring technique for removing a pattern exceeding a lithography margin (lithography margin unachieved pattern) is developed. In addition thereto, a flow of layout processing is developed every device.
However, in order to cope with the latter case, since the design technique with which the timing convergence has been given a top priority has been made until now, any of primary factors making trade-off with the timing does not exist.
Here, repeater inserting processing is known as one of the timing convergence processing exerting an influence on a layout. The repeater is inserted into the middle of the wiring as may be necessary for the purpose of adjusting a delay in the wiring. Thus, a wiring pattern is divided into parts in a stage of a design, and an element such as a buffer is inserted between the parts obtained by dividing the wiring pattern, thereby adjusting a parasitic resistance and a parasitic capacitance of the wiring. The repeater is inserted when delay calculation after completion of RC extracting processing shows that there is a timing error. In this case, however, the layout changes after completion of cutting of the wiring because the wiring in the repeater insertion position is cut. For this reason, it is necessary to confirm whether or not the lithography unachieved pattern exists in the layout after completion of the processing.
Japanese Patent Laid-Open No. 2003-132111 proposes a technique about this respect. This technique is described as follows. RC networks obtained in consideration of a dispersion of wiring widths and wiring intervals are enumerated, sizes of a buffer and a transistor are changed based on a waveform of an input signal to a circuit, and finally one, having a minimum delay, of the RC networks thus obtained is selected to be adopted as a wiring layout.
In addition, Japanese Patent Laid-Open No. Hei 11-40785 discloses a technique with which a functional block exerting an influence on a timing is determined after a path exerting an influence after completion of delay calculation and timing verification is retrieved, and a buffer insertion optimal portion is retrieved. Moreover, there is also proposed a technique for changing connection of a wiring receiving an influence exerted thereon due to the buffer insertion.